1. Field of the Invention
This invention relates to semiconductor memory devices and, in particular, to dynamic random access memory devices (DRAMs) arranged in banks for providing increased data access speed and data throughput.
2. Description of the Related Art
There is an ever increasing need for access speed and throughput in a memory device to meet the demands of ever faster generations of processors. One common type of memory device used with processors is a dynamic random access memory (DRAM). DRAMs comprise an array of individual memory cells. The memory array consists of a multitude of rows and columns, where the intersection of each row and column defines a memory cell. Typically, each DRAM memory cell comprises a capacitor for holding a charge and an access transistor for accessing the capacitor charge. The charge is representative of a data bit and can be either high voltage or low voltage (representing, e.g., a logical "1" or a logical "0", respectively). Data can be stored in memory during write operations or read from memory during read operations.
DRAMs are usually classified by the number of data paths or input/outputs (I/Os) they provide. The data paths are passageways for information to travel to and from the DRAM. When information is being written to the memory, these paths function as input paths, when information is being read from the memory, these paths function as outputs. As is evident, the more data paths, the greater the throughput of the memory. DRAMs which have 16 or more data paths (I/Os) are often referred to as "wide" DRAMs.
Refresh, read, and write operations in present-day DRAMs are typically performed for all cells in one row simultaneously. Data is read from a memory cell by activating a row, referred to as a word line, which couples all memory cells corresponding to that row to digit or bit lines which define the columns of the array. When a particular word (row) line is activated, sense amplifiers detect and amplify the data present on an active bit (column) line. In order to access a particular bit (memory cell) in the memory array, the DRAM operating system selects the particular row and column corresponding to that bit, and the sense amplifier determines whether a "1" or a "0" has been stored in the memory location. The operation of DRAM sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and U.S. Pat. No. 5,042,011, all assigned to Micron Technology Inc. and incorporated by reference herein.
It is well known in the art to arrange the memory cells of a DRAM into operative units, also referred to as memory banks. In such a structure, separate banks of memory cells are arranged to feed into a common data path. An example of this type of architecture in shown in FIG. 1.
FIG. 1 shows a multi-bank DRAM which includes two banks of memory cells, namely B0 and B1. Each bank also includes several memory cell sub-banks 50, e.g. each bank B0 and B1 includes 8 respective sub-banks arranged into groups of four (B0a, B0b, B1a, B1b) in the FIG. 1 architecture. These groups will hereinafter be referred to as the "a" and "b" groups. The sub-banks 50 each have respective row decoders 30 and sense amplifier lines 10, which separate the sub-banks 50 from one another. The sense amplifier lines 10, as is well known in the art, sense and amplify the signals present on the bit lines (i.e. the columns of the memory array). The DRAM shown in FIG. 1 is of the "wide" type, providing 16 data lines for input and output functions, arranged in a data path area 40, located between the memory banks B0 and B1.
Each bank B0, B1 includes a separate column decoder 20 for addressing a particular column or set of columns in the bank. The columns of the bank are also referred to as bit lines because they provide a path for the bits of information to travel to and from the memory cells. The column decoder 20 receives an address from an address buffer (not shown) or similar device which specifies the particular column or columns which will be addressed. The column decoder, in turn, activates particular columns of the memory array depending on the address which is specified. By "activates" it is meant that a voltage is applied to one end of the column line in order to make it active.
Each bank B0, B1 also includes three row decoders 30 for addressing a particular row within a sub-bank 50. The row decoders 30 also receive an address from an address buffer (not shown), and energize a particular row in a sub-bank depending on the address specified. The energizing of a row serves to turn on all the gates of the transistors located in that row, thereby allowing cell access. The manner in which the row decoders operate to address a given group of sub-banks (e.g. B0a, B0b, B1a, B1b) is illustrated in FIG. 4. The outside row decoders 31 address word lines in their respective sub-banks (B0a, B0b, B1a, B1b), while the interior row decoder 32 addresses word lines in both adjacent sub-banks.
The data path 40 provides a plurality of input/output (I/O) lines, shown as 41, which serve to read data from and write data to the memory sub-banks. As stated above, in the particular DRAM illustrated, 16 I/O lines are provided, but prior art DRAMs presently exist with up to 1024 I/O lines. As shown in FIG. 3, when the particular rows and columns from which data is to be retrieved are energized by the row and column decoders, the sense amplifier lines 10 determine the content of each memory location and output either a "1" or a "0". These outputs are relayed to out board logic circuitry by the, e.g. 16, I/O lines which are located in the data path 40.
In the particular device illustrated in FIGS. 1, 3, or 4, the column decoder is simultaneously addressing 8 bit lines at a time in each of two non-adjacent sub-banks located within the same bank (B0 or B1). Further, only one group of sub-banks "a" or "b" within a selected bank is addressed at a time. This means that either a first and third, or a second and fourth sub-banks, in either group "a" or "b", are energized at any one time. This is accomplished by enabling two "column select" lines through the column decoder. Each "column select" line energizes 4 physical columns within each of the two selected non-adjacent sub-banks. The row decoder, at the same time, addresses one row in each of the two selected sub-banks. In other words, the column and row decoders together specify 8 columns in each of the two non-adjacent selected sub-banks, with each column providing 1 bit, for a total of 8 bits per sub-bank. Since two sub-banks are being simultaneously addressed, this results in a 16 bit output from a memory bank (B0 or B1).
FIG. 3 shows a portion of one of the sub-banks 50 in either bank B0 or B1. Each time information is to be read from the memory, the row decoder 30 selects a particular row in each of two non-adjacent sub-banks 50 by sending a signal on the particular word line, for example WL0 in each sub-bank, which energizes the gates of all the transistors in that row. Once the particular row has been energized, the voltage stored on the capacitors of the associated transistors, in this case capacitors C1-C4, discharges onto the bit lines and travel towards the sense amplifiers located at the top and bottom of the selected sub-banks. Again for simplicity, only the sense amplifiers located above the sub-bank are shown in FIG. 3. The sense amplifiers detect the signals present on each bit line BL0-BL3 and translate them to either a logic "1" or logic "0", depending upon the voltage stored on the capacitor. The column decoder 20 then chooses a particular column or columns by sending a column select signal to the transistors T0-T3. In this case, the column decoder 20 addresses 8 bit lines at a time by sending two "column select" signals. However, for simplicity, FIG. 3 only shows 4 of the bit lines being addressed, namely BL0-BL3. This corresponds to the activation of one "column select" line. The data is placed on lines D0-D3 and run through a DC sense amplifier or helper flip-flop within the data path to output lines. Each sense amp stripe located above and below a selected sub-bank gathers 4 bits of data, for a total of 16 bits from the two selected sub-banks.
Referring again to FIG. 1, each sense amplifier stripe provides 4 bits of data as described above for each sub-bank 50. However, the column and row decoders can only select memory locations in either the 4 "a" sub-banks located on the left of a bank or the 4 "b" sub-banks 50 located on the right of the bank. Moreover, only bank B0 or B1 can be addressed at a time. This is because there is a limited number of addresses pins incoming to the memory device to address the different memory locations. The limited number of address pins only allows 2 rows and 8 columns to be addressed for the either of the "a" or "b" sub-banks, in either bank B0 or B1. Thus, the total number of bits that are provided on the data path at any one time in the prior art FIG. 1 arrangement is 16. It would be desirable to output larger numbers of bits simultaneously from the multi-bank memory device illustrated in FIG. 1.